NXP Semiconductors /MIMXRT1062 /IOMUXC /SW_MUX_CTL_PAD_GPIO_B0_12

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_B0_12

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_B0_12 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: LCD_DATA08 of instance: lcdif

1 (ALT1): Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: xbar1

2 (ALT2): Select mux mode: ALT2 mux port: ARM_TRACE_CLK of instance: cm7_mx6rt

3 (ALT3): Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO12 of instance: flexio2

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: gpio2

6 (ALT6): Select mux mode: ALT6 mux port: SRC_BOOT_CFG08 of instance: src

8 (ALT8): Select mux mode: ALT8 mux port: ENET2_TDATA00 of instance: enet2

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_B0_12

Links

() ()